Voltage controlled oscillators (VCOs) are widely used in a variety of applications where a frequency controlled oscillator is needed. In some VCO applications, it is desirable to be able to control the gain of a VCO. For example, one such application is the charge-pump phase-locked-loop (PLL). FIG. 1 is a diagram of a commonly used charge-pump PLL that is described in detail in an article entitled, “Charge-Pump Phase-Lock Loops,” by Floyd M. Gardner, IEEE Trans. Commun., Vol. COMM-28, November 1980.
In FIG. 1, an input signal having a frequency Fin is provided to one input of a phase frequency detector (PFD) 12. The other input of PFD 12 is provided from the output of a divide-by-M frequency divider 18. The PFD 12 has as outputs an Up signal and a Down signal that are provided to a corresponding Up input and Down input of a charge pump 14. When the Up input receives a signal, current Ip is sourced to the output of charge pump 14, while when the Down input receives a signal current Ip is sunk from the output of charge pump 14. The output of charge pump 14 is provided to a loop filter comprised of a resistor R1 and capacitor C1 connected in series between the output and ground, and a second capacitor C2 also connected between the charge pump output and ground. The common connection node of the charge pump output and the loop filter is connected to the input of a VCO 16. The output of VCO 16 has an oscillator frequency Fosc and is connected to the input of frequency divider 18. The flow of current Ip to/from the common connection node of the charge pump output and the loop filter causes a voltage Vctl at the input of VCO 16 to change accordingly, and thus control the frequency Fosc. The feedback loop through frequency divider to PFD 12 allows the PLL to output a frequency that is an M multiple of Fin and phase locked to Fin.
One important performance scale of a good PLL is stability with sufficient margin. A widely used rule of thumb is that the ratio Fin/LBW should be greater than 10, where LBW represents loop bandwidth. However, for a PLL having a fixed LBW, this ratio tends to be small when Fin is small. this can happen, for example, in applications where the PLL is used as a clock synthesizer when the input reference clock has a low frequency. In such instances, when Fin is sufficiently low, the fixed LBW results in compromised stability of the PLL. thus, a problem exists in the stability of the PLL when Fosc is small.